1. Field
The present application relates to a variable delay circuit and a delay amount control method.
2. Description of the Related Art
In general, in order to adjust a phase of an input signal, a delay circuit which delays an input signal by a substantially constant time is used.
Japanese Patent No. 3739525 discusses a variable delay circuit which has a first gate line, a second gate line and a plurality of switches. The first gate line is configured so that a plurality of first gates is coupled in series each other and a signal is input thereinto. The second gate line is configured so that a plurality of second gates whose delay time is different from a delay time of the first gate line are coupled in series each other. A signal delayed from the former signal is input thereinto. A plurality of switches is provided between intermediate nodes of the first gate line and corresponding intermediate nodes of the second gate line.
According to the aforementioned typical technology, when one of the plurality of switches is closed, setting intervals of delay time of the input signal changes according to a difference between delay time of the first gate and delay time of the second gate according to the number of times of passing through the first gate and the second gate. When the delay time of the first gate and the delay time of the second gate are made to be variable, the setting intervals of the delay times of the input signals change.
Japanese Patent Application Laid-Open No. 9-46196 discusses a variable delay circuit which has a first path which supplies a signal, which is inputted into an input terminal, to an output terminal, and a delay time variable second path which supplies a signal, which is input into the input terminal, to the output terminal. The second path has a function for changing delay time according to a delay time control signal. The aforementioned typical variable delay circuit selects any one of the first path and the second path according to a select signal.
According to the variable delay circuit in Japanese Patent Application Laid-Open No. 9-46196, since the delay time of the second path arbitrarily varies according to the delay time control signal, resolution power of the delay time is not limited to a specified value. According to the aforementioned typical variable delay circuit, the delay time is suitably determined by the delay time control signal, so that the resolution power of the delay time is determined to a desired value.
Japanese Patent Application Laid-Open No. 9-46197 discusses a variable delay circuit which determines a resolution power of delay time to a desired value. The aforementioned typical variable delay circuit has a plurality of delay circuits and a selector. A clock signal input into a clock input terminal, and a data signal input into a data input terminal are supplied to the plurality of delay circuits, and each of delay time of the plurality of delay circuits is difference. The selector is coupled to the plurality of delay circuits, and outputs any one of outputs from the plurality of delay circuits to a data output terminal according to a select signal.
According to the aforementioned typical variable delay circuit, the plurality of delay circuits output signals whose phases are various. When different delay circuits are selected according to the select signal, the delay time of the variable delay circuit varies according to phase difference of the output signals from the selected delay circuits.
According to the background technology in Japanese Patent Application Laid-Open No. 2006-186547, a input signal is input into the variable delay circuit which includes a minute delay section and a rough delay section are coupled in series, and a signal having any delay amount with respect to the input signal is generated.
According to the aforementioned typical technology, the minute delay section is configured so that a buffer, an additional capacity and a switch are coupled in a multi-stage. In the minute delay section, when the switch is turned on, the delay amount is increased by the additional capacity. The delay amount of the minute delay section per stage increases in comparison with the case where the switch is off.
In the rough delay section, a path which is provided with a CMOS buffer having gate delay in a multi-stage and a path which does not have gate delay are switched by each selector. As a result, the delay amount is set for each selector based on switches of each selector.
According to the aforementioned typical technology, in order to generate delay of 11 ns, for example, delay of 1 ns is generated by the minute delay section, and delay of 10 ns is generated by the rough delay section. The resolution power of the delay time becomes higher than the case where delay is generated only by the rough delay section.
Besides the aforementioned typical technology, Japanese Utility Model Application Laid-Open No. 6-10547 discusses a technology relating to a typical variable delay circuit.
According to the aforementioned typical technology, element property of the first gate, the element property of the second gate, and/or element property of the delay elements which is includes in the delay circuits influence the delay time of the first gate, the second gate and/or the delay time of the delay circuits.
According to the aforementioned typical technology, delay time is determined by a total value of the delay time of the first gate and the delay time of the second gate, or the delay time of the variable delay circuit is determined according to the delay time of the delay elements which is includes in the delay circuits. Therefore, the delay time of the variable delay circuit depends on the shortest delay time of the first and second gates.